This invention relates to an equalizing circuit for a differential sence amplifier to achieve a high sensing speed and a stable sensing operation.
For a SRAM, a sense amplifier has been normally used to sense the the data in each cell. To improve sensing speed, the equalizing technique for a sense amplifier is needed. This will now be described with reference to the FIGS. 1 to 4.
In FIG. 1, there are shown several circuit diagrams. A precharge circuit is composed with the combination of transistors T.sub.12 -T.sub.14. A SRAM cell consists of transistors T.sub.1 -T.sub.4 and resistors R.sub.1, R.sub.2. A block sense amplifier BS has the circuit arrangement composed of, in combination, transistors T.sub.15 -T.sub.39 for sensing the data in the SRAM cell. Transistors T.sub.40 -T.sub.68, in combination, compose a final sense amplifier FS which senses wholly data in other block sense amplifiers as well as the block sense amplifier BS. A data output buffer DB to store data from the final sense amplifier FS is composed, in combination, of transistors T.sub.70 -T.sub.97. A latch LA in the data output buffer DB consists of the transistors T.sub.74 -T.sub.77.
FIG. 2 is a circuit diagram showing a general address input terminal and short pulse generation circuit, in which when a latest address signal XAi has a transition, short pulse output signals SPGH and SPGL are produced by the combination circuit of transistors.
FIG. 3 is a short pulse summator in which a short pulse signal .phi.PX is produced by both a signal CS and the combination of transistors with the inputted signals SPGH and SPGL.
In the circuit configuration depicted in FIG. 4, a bit line enable signal .phi.PXBi, a sense amplifier enable signal .phi.SA and a sense amplifier equalizing signal .phi.PZ are generated. The signal .phi.PX is turned into the signal .phi.PXBi through the combination circuit of transistors T.sub.101 -T.sub.106 and a signal .phi.PY which is the summation of short pulses that a column address produces is changed into the signal .phi.PZ through the combination circuit of transistors T.sub.107 -T.sub.114. The signal .phi.PZ is changed into a sense amplifier enable signal .phi.SA, a first sense amplifier equalizing signal .phi.PZ1, and a second sense amplifier equalizing signal .phi.PZ2 through three sections A, B, and C. The section A is the sense amplifier enable signal generator composed of the combination of transistor T.sub.115 -T.sub.134. The second B with the transistors T.sub.111 -T.sub.114 and the section C with the transistors T.sub.135 -T.sub.144 are the first equalizing signal generator and the second equalizing signal generator, respectively.
The operation of the prior sense amplifier equalizing circuit with the above arrangement will now be described with reference the FIG. 6. When the extra-input address signal XAi is changed, the signal .phi.PXBi is produced. At this time, the signals .phi.PZ1, .phi.PZ2 and .phi.PZ3 are produced with the pulse width of Teq.sub.1, Teq.sub.2 and Teq.sub.3, respectively. When the signals .phi.PZ1, .phi.PZ2 and .phi.PZ3 go from high levels to low levels the signals SAO1, SAO1, SAO2, SAO2, SAO4, SAO4 and an output signal of the sense amplifier are equalized; when the signals .phi.PZ1, .phi.PZ2 and .phi.PZ3 go from low levels to high levels, the sensing of data begins; the sensing of data is completed with the transition from a high level to a low level in the signal .phi.SA.
The sensed data during a sensing cycle is stored in the latch LA existing in the data output buffer DB(FIG. 1). The width of pulses Teq.sub.1, Teq.sub.2 and Teq.sub.3 are determined by the time which is needed at least to equalize the output of the sense amplifier, normally from 7 nano-seconds to 20 nano-seconds. However, there are so many times which the equalized output is unstable because of a number of the narrow-width pulse. Accordingly, the pulse width for equalization needs to be enlarged to obtain a stable equalized signal, but there is occurred a problem that an access time is delayed. In addition, if noises have invaded during an equalizing period, the output of a sense amplifier may not be equalized in a correst way.